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900 mhz analog cordless phone baseband with compander fta suffix plastic package case 932 (lqfp48) device operating temperature package ordering information mc33411afta t a = 20 to 70 c lqfp48 semiconductor technical data order this document by mc33411a/d MC33411Bfta 1 48 1 motorola rf/if device data
the mc33411 900 mhz analog cordless phone baseband system is designed to fit the requirements of a 900 mhz analog cordless telephone system. included are three plls (phaselocked loops). two are intended for use with external vcos and 64/65 or 128/129 dual modulus prescalers, and can control the transmit and receive (lo1) frequencies for 900 mhz communication. the third pll is configured as the 2nd local oscillator (lo2), and is functional to 80 mhz. also included are muting, audio gain adjust (internal and external), low battery/carrier detect, and a wide range for the pll reference frequency. the power supply range is 2.7 to 5.5 v. oao version devices have programmable mcu clock out and reference oscillator disable functions, whereas these functions are always enabled for obo version devices. ? complete expander/compressor for superior noise rejection ? two plls and a lo suitable for a 900 mhz system ? minimal external components ? transmit path includes adjustable gain amplifier, filters, mute, compressor with bypass and limiter ? receive path contains data slicer, adjustable gain amplifier, sidetone attenuator, filters, expander with bypass, mute, volume control and power amplifier ? dual a/ds are provided to monitor rssi and v cc ? independent power amplifier with differential outputs and mute ? selectable frequency for switched capacitor filters, plls and the lo ? reference frequency source can be a crystal or system clock ? serial m p port to control gain, mute, frequency selection, phase detector gain, power down modes, low battery detect and others ? power supply range: 2.7 to 5.5 v ? power down modes for power conservation simplified block diagram v cc ds in rssi tx in rx out ds out tx out audio in mcu clock clock enable data lo2 out amp/mute compressor filter gain adj filter sidetone attn mute expander power amp programmable counters 2nd lo pll #1 pll #2 data slicer dual a/d mcu interface lpf+ vco + prescaler lpf tank this device contains 11,108 active transistors. lpf+ vco + prescaler ? motorola, inc. 1999 rev 2
mc33411a/b 2 motorola rf/if device data mod ctl mod ctl figure 1. test circuit v cc v cc v cc v cc v cc v cc v cc audio vb scf clk spi spi spi spi rssi in rx audio in ds in gnd audio lo2 out lo2 v cc lo2+ lo2 lo2 ctl lo2 gnd lo2pd lo2 gnd mco v cc audio c in c cap c out lim in tx out ds out f ref out f ref in gnd digital mcu clk out frx mc frx pll v cc rx pd pll gnd tx pd pll v cc f tx ftx mc en clk data rx out e in e cap e out pai gnd pa pao+ v cc pa vb vag mci pao tx audio alc lpf aalpf attn lpf rssi 6b a/d converter v cc 6b a/d converter 2nd lo vco 14b ctr lo2 phase detect 7b a' rx phase detect 13b n' tx phase detect 12b ref ctr mcu interface divide by 2 6b scf clk ctr mcu clk ctr 1 10 234 56789 1112 48 47 46 45 44 43 42 41 40 39 38 37 bg v ref r x gain adj rx mute data slicer inverter 36 35 34 exp pt expander 33 32 31 30 29 power amp mute power amp 28 27 26 mic amp 25 24 23 22 21 20 19 comp pt compressor limiter tx gain adj tx mute 18 17 16 15 14 13 side tone attn 7b a 13b n 0.47 m 0.47 m spi spi low max gain vol ctl v cc 1.0 k 1.0 m 100 p 5.6 p 5.62 k 0.1 m 1.0 m 0.001 m 1.0 m 1.0 m 1.0 m 1.0 m 4.99 k 4.99 k 130 1.0 m 0.1 m 4.7 0.1 m 1.0 m 47.5 k 47.5 k 1.0 m 1.0 m 1.0 m 10 k 1.0 m 0.1 m 1.0 m 0.001 m 0.001 m 0.01 m 1.0 m 0.01 m v cc 49.9 0.1 m 10 m 49.9 49.9 rf in rf in
mc33411a/b 3 motorola rf/if device data maximum ratings rating symbol value unit power supply voltage v cc 0.5 to 6.0 v junction temperature t j 6.5 to 150 c maximum power dissipation p d 150 mw notes: 1. maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the limits in the recommended operating conditions, electrical characteristics tables or pin descriptions section. 2. meets human body model (hbm) 2000 v and machine model (mm) 200 v. esd data available upon request. recommended operating conditions characteristic symbol min typ max unit supply voltage v cc 2.7 3.6 5.5 vdc operating ambient temperature t a 20 70 c input voltage low (data, clk, en) v il 0.3 v input voltage high (data, clk, en) v ih tx pll v cc 0.3 v frequency range (f ref in ) f range 4.0 18.25 mhz bandgap reference voltage v b 1.5 v dc electrical characteristics (v cc = 3.6 v, t a = 25 c, unless otherwise noted.) characteristic symbol min typ max unit static current active mode (r5/8 to 0 = 0; r6/7 = 0) act i cc 15 20 ma receive mode (r5/8, 7, 3, 2, 0 = 0; r6/7 = 0; r5/6,5,4,1 = 1) rx i cc 10 13 ma standby mode (r5/0 = 0; r6/7 = 0; r5/8 to 1 = 1) std i cc 500 1500 m a inactive mode, a only (r5/8 to 0 =1; r6/7 = 1) ina i cc 10 15 m a data slicer only ds i cc 100 m a rssi/batt a/d only ad i cc 70 m a tx audio only txa i cc 1.4 ma rx audio only rxa i cc 1.4 ma pa only pa i cc 1.0 ma 2nd lo/f ref only 2lo i cc 6.0 ma rx pll/f ref only rxpll i cc 1.0 ma tx pll/f ref only txpll i cc 1.0 ma ref osc only, oao version only rosc i cc 500 m a reference voltage, unadjusted v b 1.38 1.5 1.62 v electrical characteristics (v cc = 3.6 v, v b = 1.5 v, t a = 25 c, active mode, rx gain = 01111, vol adj = 0111, f in = 1.0 khz, unless otherwise noted.) characteristics input pin measure pin symbol min typ max unit rx audio path absolute gain (v in = 20 dbv) rx audio in e out g 4.0 0 4.0 db gain tracking (referenced to e out for v in = 20 dbv) e in e out g t db v in = 30 dbv 21 20 19 v in = 40 dbv 42 40 38 total harmonic distortion (v in = 20 dbv) rx audio in pao thd 0.7 1.0 % maximum input voltage (v cc = 2.7 v) rx audio in 11.5 dbv maximum output voltage (increase input voltage until output voltage thd = 5%, then measure output voltage) e in e out v omax 2.0 0 dbv notes: 1. values specified are pure numbers to the base 10. 2. typical performance parameters indicate the potential of the device under ideal operating conditions.
mc33411a/b 4 motorola rf/if device data electrical characteristics (continued) (v cc = 3.6 v, v b = 1.5 v, t a = 25 c, active mode, rx gain = 01111, vol adj = 0111, f in = 1.0 khz, unless otherwise noted.) characteristics unit max typ min symbol measure pin input pin rx audio path (continued) input impedance z in k w rxaudio in 600 e in 7.5 attack time e cap = 0.5 m f, r filt = 40 k e in e out t a 3.0 ms release time e cap = 0.5 m f, r filt = 40 k e in e out t r 13.5 ms compressor to expander crosstalk (v in = 10 dbv, v e in = ac gnd) mci e out c t 90 60 db rx muting (v in = 20 dbv, rx gain adj = 01111) rx audio in e out m e 84 60 db rx high frequency corner (v in = 20 dbv) scf counter = 31 d rx audio in rx out rx f ch 3.6 3.8 4.0 khz low pass filter passband ripple (v in = 20 dbv) rx audio in rx out ripple 0.4 0.6 db rx gain adjust range rx audio in rx out rx range 9.0 to 10 db rx gain adjust steps rx audio in rx out rx n 20 audio path noise, cmessage weighting (v in = ac gnd) rx audio in en dbv rx out 85 e out <95 pa out <95 volume control adjust range rx audio in e out v ctl range 14 to 16 db volume control levels e in e out v cn 16 side tone attenuate selections rx audio in rx out sta n 4 side tone attenuate (referenced to e in) e out sta db selection = 00 0.0 selection = 01 1.5 selection = 10 3.0 selection = 11 5.2 side tone attenuate threshold (c out/e in) sta thr 3.0 db power amp/mute (v cc = 3.6 v, v b = 1.5 v, t a = 25 c, active mode, f in = 1.0 khz) output swing, 5.0 ma load pai pao+ v omax 1.3 2.4 v pp (v pao+ @ 5.0 ma v pao+ @ 5.0 ma) output swing, 5.0 ma load pai pao v omax 1.3 2.4 v pp (v pao @ 5.0 ma v pao @ 5.0 ma) output swing, no load pai pao+ v omax 2.7 v pp output swing, no load pai pao v omax 2.7 v pp maximum output current pao, pao+ i omax 5.0 ma power amp mute (v in = 20 dbv, rl = 130 w ) pai pao m sp 92 60 db mic amp (v cc = 3.6 v, t a = 25 c, active mode, f in = 1.0 khz) open loop gain mci mco avol 100.000 v/v gain bandwidth mci mco gbw 100 khz maximum output swing (rl = 10 k w ) mci mco v omax 3.2 v pp notes: 1. values specified are pure numbers to the base 10. 2. typical performance parameters indicate the potential of the device under ideal operating conditions.
mc33411a/b 5 motorola rf/if device data electrical characteristics (continued) (v cc = 3.6 v, v b = 1.5 v, t a = 25 c, active mode, rx gain = 01111, vol adj = 0111, f in = 1.0 khz, unless otherwise noted.) characteristics unit max typ min symbol measure pin input pin tx audio path (v cc = 3.6 v, limiter, mutes, alc disabled, t a = 25 c, gain = 1, active mode, f in = 1.0 khz) absolute gain (v in = 10 dbv) mci tx out g 4.0 0 4.0 db gain tracking (referenced to tx out for v in = 10 dbv) mci tx out g t db v in = 30 dbv 11 10 9.0 v in = 40 dbv 17 15 13 total harmonic distortion (v in = 10 dbv) mci tx out thd 0.5 1.2 % maximum output voltage (increase input voltage until output voltage thd = 5%, then measure output voltage. tx gain adj = 8.0 db) mci tx out v omax 8.0 5.0 dbv input impedance c in z in 10 k w attack time c cap = 0.5 m f, r filt = 40 k c in tx out t a 3.0 ms release time c cap = 0.5 m f, r filt = 40 k c in tx out t r 13.5 ms expander to compressor crosstalk (v in = 20 dbv, pa no load, vc in = ac gnd) e in tx out c t 60 40 db tx muting (v in = 10 dbv) mci tx out m c 88 60 db alc output level (when enabled) mci tx out alc out dbv v in = 10 dbv 15 13 8.0 v in = 2.5 dbv 13 11 6.0 alc slope (when enabled) mci tx out slope 0.1 0.25 0.4 db/db v in = 10 dbv v in = 2.5 dbv alc input dynamic range c in tx out dr 16 to 2.5 dbv limiter output level (when enabled, v in = 2.5 dbv) lim in tx out v lim 10 7.0 dbv tx high frequency corner (v in = 10 dbv, unity gain) scf counter = 31 d lim in tx out tx f ch 3.45 3.65 3.85 khz low pass filter passband ripple (v in = 10 dbv) lim in tx out ripple 0.4 1.0 db mcu clock or scf spurs (v in = 10 dbv, relative to scf or mcu fundamental) lim in tx out 25 dbc maximum compressor gain (v in = 70 dbv) mci tx out av max db r6/8 = 0 21 r6/8 = 1 12 tx gain adjust range lim in tx out tx range 9.0 to 10 db tx gain adjust steps lim in tx out tx n 20 data amp comparator (v cc = 3.6 v, v b = 1.5 v, t a = 25 c, active or receive mode) hysteresis ds in ds out hys 20 42 60 mv threshold voltage ds in ds out v t v cc 0.7 v input impedance ds in z in 200 250 280 k w output impedance ds out z out 100 k w output high voltage (v in = v cc 1.0 v, i oh = 0 ma) ds in ds out v oh v cc audio 0.1 v cc audio v output low voltage (v in = v cc 0.4 v, i ol = 0 ma) ds in ds out v ol 0.1 0.4 v maximum frequency ds in ds out f max 10 khz notes: 1. values specified are pure numbers to the base 10. 2. typical performance parameters indicate the potential of the device under ideal operating conditions.
mc33411a/b 6 motorola rf/if device data electrical characteristics (continued) (v cc = 3.6 v, v b = 1.5 v, t a = 25 c, active mode, rx gain = 01111, vol adj = 0111, f in = 1.0 khz, unless otherwise noted.) characteristics unit max typ min symbol measure pin input pin rssi/low battery a/d (v cc = 3.6 v, v b = 1.5 v, t a = 25 c, active or receive mode) rssi voltage range rssi in spi rssi range v minimum (r5/1712 = 0) 0 interim (r5/1712 = 100000) .744 .792 maximum (r5/1712 = 1) 1.6 low battery detect operating range v cc audio spi lowb range v minimum 2.7 interim (r5/2318 = 101111) 2.7 3.1 maximum (r5/2318 = 1) 3.75 differential nonlinearity rssi in/ v cc audio spi a/d dnl 1.0 0.5 1.0 lsb resolution rssi in/ v cc audio spi resolution 6 bits input current rssi in i in 80 20 80 na reference frequency (v cc = 3.6 v, v b = 1.5 v, t a = 25 c, active mode) input current high (v in = v cc ) f ref in i ih 2.0 5.0 15 m a input current low (v in = 0 v) f ref in i il 15 5.0 2.0 m a minimum input voltage f ref in f ref in f ref out v in 300 mvpp input impedance f ref in z in 2.9 pf||11.6 k w output impedance f ref out z out 2.5 pf||4.5 k w microprocessor interface (v cc = 3.6 v, v b = 1.5 v, t a = 25 c, active or receive mode) input low voltage data/en /clk v il 0 0.3 v input high voltage data/en /clk v ih tx pll v cc 0.3 tx pll v cc v input current low (v in = 0.3 v, standby mode) data, en, clk data, en, clk i il 5.0 0.4 m a input current high (v in = 3.3 v, standby mode) data, en, clk data, en, clk i ih 1.6 5.0 m a hysteresis voltage data, en, clk data, en, clk v hys 1.0 v maximum clock frequency clk f max 2.0 mhz input capacitance data, en, clk data, clk, en c in 8.0 pf en to clk setup time en, clk t suec 200 ns data to clk setup time data, clk t sudc 100 ns hold time data, clk t h 90 ns recovery time en, clk t rec 90 ns input pulse width en, clk t w 100 ns mcu interface powerup delay t pumcu 100 m s output high voltage (i oh = 0 ma) mcu clk out v oh tx pll v cc 0.3 3.5 v notes: 1. values specified are pure numbers to the base 10. 2. typical performance parameters indicate the potential of the device under ideal operating conditions.
mc33411a/b 7 motorola rf/if device data electrical characteristics (continued) (v cc = 3.6 v, v b = 1.5 v, t a = 25 c, active mode, rx gain = 01111, vol adj = 0111, f in = 1.0 khz, unless otherwise noted.) characteristics unit max typ min symbol measure pin input pin microprocessor interface (v cc = 3.6 v, v b = 1.5 v, t a = 25 c, active or receive mode) output low voltage (i ol = 0 ma) mcu clk out v ol 0.1 0.3 v output high voltage (i oh = 0 ma) data v oh tx pll v cc 0.3 3.5 v output low voltage (i ol = 0 ma) data v ol 0.1 0.3 v rx/tx pll characteristics (v cc = 3.6 v, v b = 1.5 v, t a = 25 c, active or receive mode) output source current (v pd = 0.5 v or v cc 0.5 v) i oh m a 100 m a mode rx pd & 130 100 70 400 m a mode tx pd 520 400 280 output sink current (v pd = 0.5 v or v cc 0.5 v) i ol m a 100 m a mode rx pd & 70 100 130 400 m a mode tx pd 280 400 520 current match, 100 m a mode or 400 m a mode, v pd = v cc / 2 (i.e., 100 x (abs (i oh / i ol ))) rx pd tx pd match 80 100 125 % output off current (v pd = v cc /2), 100 m a mode or 400 m a mode rx pd tx pd i oz 80 5.0 80 na input current low (v in = 0 v) frx ftx i il 10 7.5 m a input current high (v in = v cc ) frx ftx i ih 10 14 m a input bias voltage frx ftx v bias 1.5 v output voltage high (i oh = 0 ma, voltage mode) frxmc v oh rx pll v cc 0.1 v output voltage high (i oh = 0 ma, voltage mode) ftxmc v oh tx pll v cc 0.1 v output voltage low (i ol = 0 ma, voltage mode) frxmc ftxmc v ol 0.1 v output current high (v oh = 0.8 v, current mode) frxmc ftxmc i oh 130 100 70 m a output current low (v ol = 0.8 v, current mode) frxmc ftxmc i ol 70 100 130 m a maximum input frequency frx ftx f max 20 mhz input voltage swing frx ftx v in 200 1200 mvpp modulus control prop delay frx ftx frxmc ftxmc 20 ns lo2 pll characteristics (v cc = 3.6 v, v b = 1.5 v, t a = 25 c, active mode) output source current (v pd = 0.5 v or v cc 0.5 v) lo2pd i oh m a 100 m a mode 130 100 70 400 m a mode 520 400 280 output sink current (v pd = 0.5 v or v cc 0.5 v) lo2pd i ol m a 100 m a mode 70 100 130 400 m a mode 280 400 520 current match, 100 m a mode or 400 m a mode, v pd = v cc / 2 (i.e., 100 x (abs (i oh / i ol ))) lo2pd match 80 100 125 % notes: 1. values specified are pure numbers to the base 10. 2. typical performance parameters indicate the potential of the device under ideal operating conditions.
mc33411a/b 8 motorola rf/if device data electrical characteristics (continued) (v cc = 3.6 v, v b = 1.5 v, t a = 25 c, active mode, rx gain = 01111, vol adj = 0111, f in = 1.0 khz, unless otherwise noted.) characteristics unit max typ min symbol measure pin input pin lo2 pll characteristics (v cc = 3.6 v, v b = 1.5 v, t a = 25 c, active mode) output off current (v pd = v cc /2) lo2pd i oz 80 5.0 80 na input current low (v in = 0.5 v) lo2ctl i il 1.0 0.02 m a input current high (v in = v cc 0.5 v) lo2ctl i ih 0.02 1.0 m a input voltage range lo2ctl v range 0.4 v cc v maximum 2nd lo frequency 65 80 mhz lo2 out drive (25 w load) v out 112 180 245 mvpp counters (v cc = 3.6 v, v b = 1.5 v, t a = 25 c, active mode) 12bit reference counter range [note 1] 3 to 4095 13bit n counter range [note 1] 3 to 8191 7bit a counter range [note 1] 64/65 modulus prescaler 0 to 63 128/129 modulus prescaler 0 to 127 14bit lo2 counter range [note 1] 12 to 16383 6bit counters (for scf) [note 1] 3 to 63 notes: 1. values specified are pure numbers to the base 10. 2. typical performance parameters indicate the potential of the device under ideal operating conditions. pin function description pin symbol/type description description 1 frx mc (output) frx mc 1 rx pll v cc current mode rx pll v cc voltage mode 100 m a 100 m a modulus control output for the rx pll section. can be set to output in current mode or voltage mode, selectable with bit 3/16. 2 frx (input) frx 2 pll v cc bias 80 m a 200 k receives the signal from the external 64/65 or 128/129 prescaler. dc bias is at 1.3 v. note: 1. all v cc pins must be within 0.5 v of each other.
mc33411a/b 9 motorola rf/if device data pin function description (continued) description description symbol/type pin 3 rx pll v cc (input) 3 rx pll section v cc 10 0.01 10 supply pin for the rx pll section. allowable range is 2.7 to 5.5 v and must be within 0.5 v of all other v cc pins. good bypassing is required and isolation with a 10 w resistor is recommended. 4 rx pd (output) rx pd 4 100/ 400 m a rx pll v cc 100/ 400 m a rx pll v cc 125 125 to filter rx phase detector output. the output either sources or sinks current, or neither, depending on the phase difference of the phase detector input signals. during lock, very narrow pulses with a frequency equal to the pll reference frequency are present. output current is either 100 m a or 400 m a, selectable with bit 2/20. 5 pll gnd ground pin for the pll section. a direct connection to a ground plane is strongly recommended. 6 tx pd (output) same as pin 4, except powered from tx pll v cc . tx phase detector output. description same as for pin 4, except bit 1/20 controls the current level. 7 tx pll v cc (input) 7 tx pll section, mcu serial interface, reference oscillator v cc 10 0.01 10 supply pin for the tx pll section, mcu serial interface, mcu clock counter, and the reference oscillator. allowable range is 2.7 to 5.5 v and must be within 0.5 v of all other v cc pins. good bypassing is required and isolation with a 10 w resistor is recommended. 8 ftx (input) same as pin 2. receives the signal from the external 64/65 or 128/129 prescaler. dc bias is at 1.5 v. 9 ftx mc (output) ftx mc 9 tx pll v cc current mode tx pll v cc voltage mode 100 m a 100 m a modulus control output for the tx pll section. can be set to output in a current mode or a voltage mode, selectable with bit 3/16. note: 1. all v cc pins must be within 0.5 v of each other.
mc33411a/b 10 motorola rf/if device data pin function description (continued) description description symbol/type pin 10 en (input) enable 10 tx pll v cc 240 1.0 m a enable input for the mcu interface section. hysteresis threshold is within 0.5 v of ground and v cc . see text for proper waveform required at this pin. 11 clk (input) same as pin 10. clock input for the mcu interface section. hysteresis threshold is within 0.5 v of ground and v cc . data is written or read out on clock's rising edge. maximum clock rate is 2.0 mhz. 12 data (i/o) data 12 tx pll v cc 240 1.0 m a tx pll v cc disable data data i/o line for the mcu interface section. both address and data are provided to/from this pin. input threshold is within 0.5 v of ground and v cc . data is written or read out on clock's rising edge. 13 mcu clk out (output) clk out 13 tx pll v cc 1.0 k tx pll v cc the microprocessor clock output is derived from the reference oscillator and a programmable divider with divide ratios of 2 to 312.5. it can be used to drive a microprocessor and thereby reduce the number of crystals required in the system design. the driver has an internal resistor in series with the output which can be combined with an external capacitor to form a lowpass filter to reduce radiated noise on the pcb. this output also functions as the output for the counter test modes. 1) for the mc33411a the clk out can be disabled via the mcu interface. 2) for the MC33411B this output is always active (on). 14 gnd digital ground for the data, mcu clk out, and f ref out digital outputs. a direct connection to the ground plane is strongly recommended. note: 1. all v cc pins must be within 0.5 v of each other.
mc33411a/b 11 motorola rf/if device data pin function description (continued) description description symbol/type pin 15, 16 f ref in, f ref out 16 f ref out f ref in 15 100 100 tx pll v cc tx pll v cc disable reference frequency input for various portions of the circuit, including the plls, scf clock, etc. a crystal (4 to 18.25 mhz) may be connected as shown, or an external frequency source may be capacitor coupled to pin 15. see text for crystal requirements. 1) for the mc33411a the f ref out can be disabled via the mcu interface. 2) for the MC33411B this output is always active (on). 17 ds out (output) ds out 17 v cc audio v cc audio 100 k data slicer output (open collector with internal 100 k w pullup resistor). 18 tx out (output) , 18, 20 v cc audio tx out is the tx path audio output. internally this pin has a lowpass filter circuitry with 3.0 db bandwidth of 4.0 khz. tx gain and mute are programmable through the mcu interface. this pin is sensitive to load capacitance. 20 c out (output) tx out , c out v b c out is the compressor output. 19 lim in (input) lim in 19 v cc audio 400 k v b lim in is the limiter input. this pin is internally biased and has an input impedance of 400 k w . lim in must be accoupled. 21 c cap c cap 21 v cc audio v cc audio 40 k c cap is the compressor rectifier filter capacitor pin. it is recommended that an external filter capacitor to v cc audio be used. a practical capacitor range is 0.1 to 1.0 m f. the recommended value is 0.47 m f. note: 1. all v cc pins must be within 0.5 v of each other.
mc33411a/b 12 motorola rf/if device data pin function description (continued) description description symbol/type pin 22 c in (input) c in 22 v cc audio 12.5 k v b c in is the compressor input. this pin is internally biased and has an input impedance of 12.5 k w . c in must be accoupled. 23 v cc audio (input) 23 audio section, filters, a/d converters, data slicer v cc 0.01 10 supply input for the audio section, filters, a/d converters, and data slicer. allowable range is 2.7 to 5.5 v. good bypassing is required. 24 mco (output) mco 24 audio v cc output of the microphone amplifier. maximum output swing is 3.0 v pp for v cc 3.0 v. maximum output current is >1.0 ma peak. 25 mci (input) mci 25 v cc audio 2.5 m a v b inverting input of the microphone amplifier. gain and frequency response are set with external resistors and capacitors from this pin to the audio source and to mco. 26 vag (output) vag 26 0.1 m f 30 k audio v cc analog ground for the audio section filters. vag is equal to vb and is buffered from vb. maximum current which can be sourced from this pin is 500 m a. 27 v b (output) v b 27 4.7 m f 30 k audio v cc 240 an internal 1.5 v reference for several sections. this voltage is adjustable with bits 3/2017. maximum source current is 100 m a. psrr, noise and crosstalk depends on the external capacitor. 28 v cc pa (input) 28 audio power v cc 0.01 10 supply pin for the power amplifier outputs. allowable range is 2.7 to 5.5 v. good bypassing is required. note: 1. all v cc pins must be within 0.5 v of each other.
mc33411a/b 13 motorola rf/if device data pin function description (continued) description description symbol/type pin 29 pao+ (output) pao+ 29 audio v cc output of the second power amplifier. this amplifier is set for unity inverting gain and is driven by pao. maximum swing is 2.9 v pp and maximum output current is >5.0 ma peak. dc level is 1.5 v. 30 pao (output) same as pin 29. output of the first power amplifier. its gain is set with external resistors and capacitors from this pin to pai. output capability is the same as pin 28. 31 gnd pa ground pin for the power amplifier outputs. a direct connection to a ground plane is strongly recommended. 32 pai (input) pai 32 v cc audio 2.5 m a v b inverting input of the power amplifier. gain and frequency response are set with external resistors and capacitors from this pin to the audio source and to pao. 33 e out (output) rx audio output 33 audio v cc v b expander output. this output is sensitive to load capacitance. maximum output signal level is 2.5 v pp . maximum output current is >1.0 ma. 34 e cap e cap 34 v cc audio v cc audio 40 k e cap is the expander rectifier filter capacitor pin. connect an external filter capacitor between v cc audio and e cap . the recommended capacitance range is 0.1 to 1.0 m f. the suggested value is 0.47 m f. 35 e in (input) e in 35 v cc audio v b 30 k the expander input pin is internally biased and has input impedance of 30 k w . 36 rx out (output) rx out 36 v cc audio v b rx out is the rx audio output. an internal lowpass filter has a 3.0 db bandwidth of 4.0 khz. note: 1. all v cc pins must be within 0.5 v of each other.
mc33411a/b 14 motorola rf/if device data pin function description (continued) description description symbol/type pin 37 rssi in (input) rssi in 37 v cc audio voltage input to rssi a/d converter. full scale is 0 to 1.6 v. 38 rx audio in (input) rx audio in 38 v cc audio 600 k v b rc network input to the rx audio path. input impedance is 600 k w . input signal must be capacitor coupled 39 ds in (input) ds in 39 v cc audio 250 k 250 k input for the digital data from the rf receiver section. input impedance is 250 k w . hysteresis is internally provided. input signal level must be between 50 and 700 mvpp. 40 gnd audio ground pin for the audio section. a direct connection to a ground plan is strongly recommended. 41 lo2 out (output) lo2 out 41 lo2 v cc lo2 v cc lo2 v cc 50 2.5 ma buffered output of the 2nd lo. this high frequency output is a current, requiring an external pullup resistor. 42 lo2 v cc (input) 42 lo2 section v cc 10 0.01 10 supply pin for the lo2 section. allowable range is 2.7 to 5.5 v and must be within 0.5 v of all other v cc pins. good bypassing is required and isolation with a 10 w resistor is recommended. note: 1. all v cc pins must be within 0.5 v of each other.
mc33411a/b 15 motorola rf/if device data pin function description (continued) description description symbol/type pin 43, 45 lo2+, lo2 lo2+ 43 lo2 v cc lo2 v cc the 2nd lo. external tank components are required. the internal capacitance across the pins is adjustable from 0 to 7.6 pf for fine tuning performance with bits 7/2018. 44 lo2 ctl (input) lo2 45 lo2 ctl 44 lo2 v cc 55 k lo2 control is the dc control input for this vco. typically it is the output of the lowpass filter fed from the phase detector output. 46 lo2 gnd ground pin for the lo2 section. a direct connection to a ground plane is strongly recommended. 47 lo2pd (output) lo2 pd 47 100/ 400 m a lo2 pll v cc 100/ 400 m a lo2 pll v cc 125 125 to filter lo2 phase detector output. the output either sources or sinks current, or neither, depending on the phase difference of the phase detector input signals. during lock, very narrow pulses with a frequency equal to the pll reference frequency are present. output current is either 100 m a or 400 m a, selectable with bit 3/14. 48 lo2 gnd ground pin for the lo2 section. a direct connection to a ground plane is strongly recommended. note: 1. all v cc pins must be within 0.5 v of each other.
mc33411a/b 16 motorola rf/if device data functional description the following text, graphics, tables and schematics are provided to the user as a source of valuable technical information about the mc33411. this information originates from thorough evaluation of the device performance. this data was obtained by using units from typical wafer lots. it is important to note that the forgoing data and information was from a limited number of units. by no means is the user to assume that the data following is a guaranteed parametric. only the minimum and maximum limits identified in the electrical characteristics tables found earlier in the spec are guaranteed. note: in the following descriptions, control bits in the mcu serial interface for the various functions will be identified by register number and bit number. for example, bit 3/19 indicates bit 19 of register 3. bits 5/1411 indicates register 5, bits 14 through 11. please refer to figure 1. general circuit description the mc33411a/b is a low power baseband ic designed to interface with the mc13145 uhf wideband receiver and mc13146 transmitter for applications up to 2.0 ghz. the devices are primarily designated to be used for 900 mhz ism band in a ct900, low power, dual conversion cordless phone, but other applications such as data links with analog processing could be developed. this device contains complete baseband transmit and receive processing sections, a transmit and receive pll section, a programmable pll second local oscillator usable to 80 mhz, rssi and low battery detect circuitry and serial interface for a microprocessor. oao versions of the device have the ability to disable either the reference oscillator or mcu clock outputs. this feature is useful for systems where the mcu has an internal clock, allowing the user to place the mc33411 into inactive (lowest power consumption) mode. the oao version is also useful for systems where the mcu has a dedicated clock source, allowing for lower power consumption from the mc33411 by disabling the mcu clock output. obo versions of the device are intended for systems where the mcu clock will always be driven from the mc33411. these bits are purposefully ohardwiredo to the enable state to ensure proper operation of the reference oscillator and mcu clock output even during battery discharge/recharge cycles. all internal registers are completely static no refreshing is required under normal operation conditions. dc current figures 2 through 5 are the current consumption for inactive (mc33411 oao version only), standby, receive, and active modes versus supply voltages. figures 6 and 7 show the typical behavior of current consumption in relation to temperature. figure 8 illustrates the effect of the mcu clock output frequency to supply current during active mode. 0 supply current (ma) 1.8 2.7 6.0 2.7 supply voltage (v) s uppl y c u rren t ( a) figure 2. supply current versus supply voltage (inactive mode) supply voltage (v) figure 3. supply current versus supply voltage (standby mode) 5.0 4.0 3.0 2.0 1.0 3.1 3.5 3.9 4.3 4.7 5.5 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.0 3.1 3.5 3.9 4.3 5.1 5.5 t a = 25 c t a = 25 c 5.1 m 4.7 mcu clock off
mc33411a/b 17 motorola rf/if device data s uppl y c u rren t ( m a) 10 2.7 supply voltage (v) t a = 25 c figure 4. supply current versus supply voltage (receive mode) 9.5 9.0 8.5 8.0 7.5 3.1 3.5 3.9 4.3 4.7 5.1 5.5 11 14 2.7 supply current (ma) figure 5. supply current versus supply voltage (active mode) supply voltage (v) t a = 25 c 13 12 3.5 5.5 figure 6. supply current versus temperature normalized to 25 c (standby mode) v cc = 3.6 v figure 7. supply current versus temperature normalized to 25 c (receive & active mode) v cc = 3.6 v 12.5 30 supply current (ma) mcu clk out (khz) figure 8. supply current versus mcu clock output frequency (active mode) v cc = 3.6 v t a = 25 c 2030 5030 12.3 12.1 11.9 11.7 11.5 mcu clock out off mcu clock out on 3.1 3.9 4.3 4.7 5.1 mcu clock out on mcu clock out off 1030 3030 4030 20 20 740 20 i cc , (ma) degrees ( c) i cc , ( a) degrees ( c) 0257085 720 700 680 660 640 620 600 m 19 18 17 16 15 14 13 12 11 10 5.0 10 25 40 55 70 85 active receive
mc33411a/b 18 motorola rf/if device data table 1. tx gain adjust programming (register 7) gain control bit #9 gain control bit #8 gain control bit #7 gain control bit #6 gain control bit #5 gain ctl # gain/attenuation amount <6 9.0 db 0 0 1 1 0 6 9.0 db 0 0 1 1 1 7 8.0 db 0 1 0 0 0 8 7.0 db 0 1 0 0 1 9 6.0 db 0 1 0 1 0 10 5.0 db 0 1 0 1 1 11 4.0 db 0 1 1 0 0 12 3.0 db 0 1 1 0 1 13 2.0 db 0 1 1 1 0 14 1.0 db 0 1 1 1 1 15 0 db 1 0 0 0 0 16 1.0 db 1 0 0 0 1 17 2.0 db 1 0 0 1 0 18 3.0 db 1 0 0 1 1 19 4.0 db 1 0 1 0 0 20 5.0 db 1 0 1 0 1 21 6.0 db 1 0 1 1 0 22 7.0 db 1 0 1 1 1 23 8.0 db 1 1 0 0 0 24 9.0 db 1 1 0 0 1 25 10 db >25 10 db transmit speech processing system this portion of the audio path goes from otx audioo to otx outo. the gain of the microphone amplifier is set with external resistors to receive the audio from the microphone hybrid or any other audio source. the mco output has railtorail capability. the otx audioo pin will be accoupled. the audio transmit signal path includes automatic level control (alc) (also referred to as the compressor), tx mute, limiter, filters, and tx gain adjust. the alc provides osofto limiting to the output signal swing as the input voltage slowly increases. with this technique the gain is slightly lowered to help reduce distortion of the audio signal. the limiter section provides hard limiting due to rapidly changing singal levels, or transients. the alc, tx mute, and limiter functions can be enabled or disabled vis the mcu serial interface. the tx gain adjust can also be remotely controlled to set different desired signal levels. the adjustable gain stage provides 20 levels of gain in 1.0 db increments. it is controlled with bits 7/95 as shown in table 1. the effect of the gain setting under various alc/limiter on/off settings is shown in figure 9. the lowpass filter before the gain stage is a switched capacitor filter with a corner frequency at 3.7 khz. this frequency is dependent upon the scf clock, nominaly set to 165 khz and is directly proportional to the scf clock. the filter response for inband, ripple, wideband, as well as phase and group delay, are shown in figures 10 through 14. the mute switch at pin 18 will mute a minimum of 60 db. bit 6/2 controls the mute. the limiter can be disabled by programming a logic 1 into 6/5. the compressor with alc transfer characteristic is shown in figure 15. the alc gain is controlled by bits 6/1112. if both bits are progr ammed to a logic 0, the alc gain is set to 5.0 db. if bit 6/11 is set to a logic 1, the alc gain will be set to 10 db, whereas if bit 6/12 is set to a logic 1 the alc gain will be 25 db. the alc function may be disabled by programming a logic 1 into bit 6/6. the compressor low maximum gain can be set with bit 6/8. programming this bit to a logic 0 sets the maximum gain to 23 db. a lower maximum gain, nominally 13.5 db, is achieved by programming the bit to a logic 1. the entire compressor can be bypassed (i.e., 0 db) by programming bit 6/4 to a logic 1. figures 16 through 22 describe the characteristics of the compressor, alc, and limiter.
mc33411a/b 19 motorola rf/if device data 10 12 9.0 tx gain setting (db) max tx out v oltag e (d bv ) 2.0 0 2.0 4.0 6.0 8.0 14 16 18 20 1.0 11 figure 9. tx audio output voltage versus gain control setting 5.0 100 f, frequency (hz) figure 10. lim in to tx out gain versus frequency (inband) v cc = 3.6 v t a = 25 c v in = 10 dbv voltage gain (db) 0 5.0 10 15 20 25 30 35 40 45 50 55 1000 10000 100 1.5 0 100 f, frequency (hz) v oltag e gai n (d b ) figure 11. lim in to tx out gain versus frequency (ripple) f, frequency (hz) figure 12. lim in to tx out gain versus frequency (wideband) v cc = 3.6 v t a = 25 c v in = 10 dbv 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1000 10000 v cc = 3.6 v t a = 25 c v in = 10 dbv 100 1000 1000000 voltage gain (db) 10 20 30 40 50 60 70 80 90 10 10000 100000 10 100 180 100 group delay (ms) f, frequency (hz) f, frequency (hz) figure 13. lim in to tx out phase versus frequency figure 14. lim in to tx out group delay versus frequency v cc = 3.6 v t a = 25 c v in = 10 dbv pha se (d egrees ) 135 90 45 0 45 90 135 180 1000 10000 v cc = 3.6 v t a = 25 c v in = 10 dbv 1000 10000 1.0 0.1 0 3.0 7.0 alc on, limiter on/off alc off, limiter off alc off, limiter on 7.0 5.0 1.0 3.0 5.0 9.0 v cc = 3.6 v t a = 25 c v in = 10 dbv
mc33411a/b 20 motorola rf/if device data 0 60 50 40 30 20 10 0 10 5.0 10 15 20 25 30 35 40 4.0 3.0 2.0 1.0 0 distortion (%) tx out voltage (dbv) c in (dbv) 30 20 33 23.5 v in > = 4.0 dbv, v out = 1.26 v pp (rapidly changing limited signals) v in = 16 dbv, v out = 13 dbv (slowly changing alc signals) v in = 2.5 dbv, v out = 10 dbv acomp low max gain eno = 1.0 maximum gain = 12 acomp low max gain eno = 0 maximum gain = 21 60 50 40 30 20 10 0 50 40 30 20 10 0 c out (dbv) 0 60 0 60 mci voltage (dbv) tx out voltage (dbv) mci voltage (dbv) mci voltage (dbv) c out voltage (dbv) c in voltage (dbv) figure 15. compressor characteristic with programmable compressor maximum gain figure 16. tx audio compressor response (distortion & amplitude, alc off, lim off) figure 17. tx audio compressor response (distortion & amplitude, alc off, lim off) figure 18. tx output audio response (lim & alc off) figure 19. tx output audio response (lim on, alc off) figure 20. tx output audio response (lim off, alc on) 50 40 30 20 10 0 10 5.0 10 15 20 25 30 35 40 4.0 3.0 2.0 1.0 0 distortion (%) 50 40 30 20 10 0 10 5.0 10 15 20 25 30 35 40 45 14 10 6.0 2.0 0 4.0 8.0 12 distortion (%) compressor transfer distortion v cc = 3.6 v t a = 25 c r6/8 = 0 v cc = 3.6 v t a = 25 c v cc = 3.6 v t a = 25 c v cc = 3.6 v t a = 25 c distortion distortion tx out tx out v cc = 3.6 v t a = 25 c r6/8 = 1 0 60 c out voltage (dbv) c in voltage (dbv) 50 40 30 20 10 0 10 5.0 10 15 20 25 30 35 40 45 14 10 6.0 2.0 0 4.0 8.0 12 compressor transfer distortion tx out voltage (dbv) distortion (%) 0 60 50 40 30 20 10 0 10 5.0 10 15 20 25 30 35 40 4.0 3.0 2.0 1.0 0 distortion (%) distortion tx out
mc33411a/b 21 motorola rf/if device data 0 60 50 40 30 20 10 0 10 5.0 10 15 20 25 30 35 40 4.0 3.0 2.0 1.0 0 distortion (%) tx out voltage (dbv) mci voltage (dbv) mci voltage (dbv) figure 21. tx output audio response (lim off, r6/11 = 1) figure 22. tx output audio response (lim off, r6/12 = 1) v cc = 3.6 v t a = 25 c v cc = 3.6 v t a = 25 c distortion tx out tx out voltage (dbv) 0 60 50 40 30 20 10 0 10 5.0 10 15 20 25 30 35 40 4.0 3.0 2.0 1.0 0 distortion (%) distortion tx out data slicer the data slicer will receive the low level digital signal from the rf receiver section at pin 39. the input signal to the data slicer must be >200 mvpp. hysteresis of 40 mv is internally provided. the output of the data slicer will be same waveform, but with an amplitude of 0 to v cc , and can be observed at pin 17 if bits 5/98 are set to 00. the output can be inverted by setting bit 5/9 = 1. the data slicer can be disabled by setting bit 5/8 = 1. receive audio path the receive audio path (pins 38, 3633) consists of an antialiasing filter, a lowpass filter, side tone attenuator, gain adjust stage, a mute switch, expander and volume control. the switched capacitor lowpass filter is an 8 pole filter, with a corner frequency at 3.8 khz. this is designed to provide bandwidth limiting in the audio range. the gain stage provides 20 db of gain adjustment in 1.0 db steps, measured from pin 38 to 36. bits 7/40 are used to set the gain according to table 3. the mute switch, controlled by bit 6/1, will mute a minimum of 60 db. when the compressor output is within 3.0 db of the expander input level, the rx output (pin 36) can be attenuated (referenced to the expander output) by bits 6/109. for 6/109 = 00, the attenuation is 0 db. for the other combinations, 6/109 = 01, attenuation = 3.0 db; 6/109 = 10, attenuation = 6.0 db; and 6/109 = 11, attenuation = 10.4 db (see table 2). the expander can be bypassed by setting bit 6/3 = 1. table 3 shows the various gain control settings which can be accessed in register 7. table 4 is the volume control settings, also located in register 7. figures 23 through 31 illustrate the various characteristics of the reveive audio path. table 2. side tone attenuate programming side tone attenuate bit #1 side tone attenuate bit #0 select # side tone attenuate amount at expander input side tone attenuate amount at expander output 0 0 0 0 db 0 db 0 1 1 1.5 db 3.0 db 1 0 2 3.0 db 6.0 db 1 1 3 5.2 db 10.4 db table 3. rx gain adjust programming (register 7) gain control bit #4 gain control bit #3 gain control bit #2 gain control bit #1 gain control bit #0 gain ctl # gain/attenuation amount <6 9.0 db 0 0 1 1 0 6 9.0 db 0 0 1 1 1 7 8.0 db 0 1 0 0 0 8 7.0 db 0 1 0 0 1 9 6.0 db 0 1 0 1 0 10 5.0 db 0 1 0 1 1 11 4.0 db 0 1 1 0 0 12 3.0 db 0 1 1 0 1 13 2.0 db
mc33411a/b 22 motorola rf/if device data table 3. rx gain adjust programming (register 7) (continued) gain control bit #4 gain/attenuation amount gain ctl # gain control bit #0 gain control bit #1 gain control bit #2 gain control bit #3 0 1 1 1 0 14 1.0 db 0 1 1 1 1 15 0 db 1 0 0 0 0 16 1.0 db 1 0 0 0 1 17 2.0 db 1 0 0 1 0 18 3.0 db 1 0 0 1 1 19 4.0 db 1 0 1 0 0 20 5.0 db 1 0 1 0 1 21 6.0 db 1 0 1 1 0 22 7.0 db 1 0 1 1 1 23 8.0 db 1 1 0 0 0 24 9.0 db 1 1 0 0 1 25 10 db >25 10 db table 4. volume control programming volume control bit #13 volume control bit #12 volume control bit #11 volume control bit #10 volume ctl # gain/attenuation amount 0 0 0 0 0 14 db 0 0 0 1 1 12 db 0 0 1 0 2 10 db 0 0 1 1 3 8.0 db 0 1 0 0 4 6.0 db 0 1 0 1 5 4.0 db 0 1 1 0 6 2.0 db 0 1 1 1 7 0 db 1 0 0 0 8 2.0 db 1 0 0 1 9 4.0 db 1 0 1 0 10 6.0 db 1 0 1 1 11 8.0 db 1 1 0 0 12 10 db 1 1 0 1 13 12 db 1 1 1 0 14 14 db 1 1 1 1 15 16 db
mc33411a/b 23 motorola rf/if device data 180 100 phase (degrees) f, frequency (hz) v cc = 3.6 v t a = 25 c v in = 20 dbv 1000 100 0 135 90 45 0 45 90 135 180 10 100 f, frequency (hz) v cc = 3.6 v t a = 25 c v in = 20 dbv v oltag e gai n (d b ) 0 10 20 30 40 50 60 70 80 90 100 1000 10000 100000 1000000 0.7 0.3 f, frequency (hz) v cc = 3.6 v t a = 25 c v in = 20 dbv 100 1000 100 0 voltage gain (db) 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 55 5.0 100 v oltag e gai n (d b ) f, frequency (hz) v cc = 3.6 v t a = 25 c v in = 20 dbv 0 5.0 10 15 20 25 30 35 40 45 50 1000 10000 1.4 14 2.0 9.0 max e out voltage (dbv) volume setting (db) max r x out v oltag e (d bv ) figure 23. rx out maximum output voltage versus gain control setting rx gain setting (db) figure 24. e out maximum output voltage versus volume control setting figure 25. rx audio in to rx out gain versus frequency (inband) figure 26. rx audio in to rx out gain versus frequency (ripple) figure 27. rx audio in to rx out gain versus frequency (wideband) figure 28. rx audio in to rx out phase versus frequency 10 6.0 2.0 2.0 6.0 10 14 1.2 1.0 0.8 0.6 0.4 7.0 5.0 3.0 1.0 1.0 3.0 5.0 7.0 9.0 11 0 2.0 4.0 6.0 8.0 10 12 14 16 18 20 v cc = 3.6 v t a = 25 c v cc = 3.6 v t a = 25 c
mc33411a/b 24 motorola rf/if device data 10 100 f, frequency (hz) v cc = 3.6 v t a = 25 c v in = 20 dbv 1.0 0.1 0 1000 10000 group delay (ms) 10 100 5.0 40 voltage gain (db) f, frequency (hz) e out voltage (dbv) e in voltage (dbv) figure 29. rx audio in to rx out group delay versus frequency figure 30. aalpf response gain versus frequency figure 31. e in to e out transfer curve 1000 10000 100000 1000000 0 10 20 30 40 50 60 70 80 90 100 v cc = 3.6 v t a = 25 c v in = 20 dbv scf clk = 2.5 mhz scf corner = 57 khz 35 30 25 20 15 10 5.0 0 5.0 15 25 35 45 55 65 expander transfer distortion 28 24 20 16 12 8.0 4.0 0 distortion (%) v cc = 3.6 v t a = 25 c
mc33411a/b 25 motorola rf/if device data power amplifiers the power amplifiers (pins 29, 30, 32) are designed to drive the earpiece in a handset, or the telephone line via a hybrid circuit in the base unit. each output (pao+ and pao) can source and sink 5.0 ma, and can swing 1.3 v pp each. for high impedance loads, each output can swing 2.7 v pp (5.4 v pp differential). the gain of the amplifiers is set with a feedback resistor from pin 30 to 32, and an input resistor at pin 32. the differential gain is 2x the resistor ratio. capacitors can be used for frequency shaping. the pins' dc level is vb ( @ 1.5 v). the mute switch, controlled with bit 6/0, will provide 60 db of muting with a 50 k w feedback resistor. the amount of muting will depend on the value of the feedback resistor. figures 32 and 33 show the power amplifier swing/distortion for v cc = 3.6 v, and figure 34 illustrates the maximum swing capability for various value of v cc . 0 3.2 0 pai (v pp ) 2.0 1.2 0 2.4 4.4 pao ( v ) 20 3.5 2.5 pao (distortion %) pai (v pp ) v cc (v) figure 32. power amplifier maximum output swing figure 33. power amplifier distortion figure 34. power amplifier maximum output swing versus v cc 0.4 0.8 1.2 1.6 2.0 2.8 3.2 3.6 4.0 0.4 0.8 1.6 2.4 2.8 pp open 130 w open 2.4 4.4 0.4 0.8 1.2 1.6 2.0 2.8 3.2 3.6 4.0 15 10 5.0 0 130 w v cc = 3.6 v t a = 25 c v cc = 3.6 v t a = 25 c pao ( v ) pp 3.0 2.5 2.0 1.5 1.0 0.5 0 3.0 3.5 4.0 4.5 5.0 5.5 open 130 w t a = 25 c
mc33411a/b 26 motorola rf/if device data reference oscillator/mcu clk out the reference oscillator provides the frequency basis for the three plls, the switched capacitor filters, and the mcu clock output. the source for the reference clock can be a crystal in the range of 4.0 to 18.25 mhz connected to pins 15 & 16, or it can be an external source connected to f ref in (pin 15). the reference frequency is directed to: a. a programmable 12bit counter (register bits 4/110) to provide the reference frequency for the three plls. the 12bit counter is to be set such that, in conjunction with the programmable counters within each pll, the proper frequencies can be produced by each vco. b. a programmable 6bit counter (register bits 4/1712), followed by a 2 stage, to set the frequency for the switched capacitor filters to 165 khz, or as close to that as possible. c. a programmable 3bit counter (register bits 7/1614) which provides the mcu clock output (see tables 5 and 6). a representation of the reference oscillator is given by figures 35 and 36. figure 35. reference oscillator schematic reference oscillator r pi c pi r po c po gm f ref in f ref out xtal c 2 c 1 figure 36. reference oscillator input and output impedance input impedance (r pi // c pi ) 11.6 k w // 2.9 pf output impedance (r po // c po ) 4.5 k w // 2.5 pf figures 37 and 38 show a typical gain/phase response of the oscillator. load capacitance (c l ), equivalent series resistance (esr), and even supply voltage will have an effect on the oscillator response as shown in figures 39 and 40. it should be noted that optimum performance is achieved when c1 equals c2 (c1/c2 = 1). figure 41 represents the esr versus crystal load capacitance for the reference oscillator. this relationship was defined by using a 6.0 db minimum loop gain margin at 3.6 v. this is considered the minimum gain margin to guarantee oscillator startup. oscillator startup is also significantly affected by the crystal load capacitance selection. in figure 39, the relationship between crystal load capacitance and esr can be seen. the lower the load capacitance the better the performance. given the desired crystal load capacitance, c1 and c2 can be determined from figure 42. it should also be pointed out that current consumption increases when c1 c2. be careful not to overdrive the crystal. this could cause a noise problem. an external series resistor on the crystal output can be added to reduce the drive level, if necessary.
mc33411a/b 27 motorola rf/if device data 100 10.237 16 10.237 f, frequency (mhz) f, frequency (mhz) phase (degrees) v oltag e gai n (d b ) 14 12 10 8.0 6.0 4.0 2.0 0 2.0 4.0 10.238 10.239 10.240 10.241 10.242 10.243 10.238 10.239 10.240 10.241 10.242 10.24 80 60 40 20 0 20 40 60 80 100 v cc = 3.6 v t a = 25 c 10.24 mhz, 10 pf load capacitance crystal v cc = 3.6 v t a = 25 c 10.24 mhz, 10 pf load capacitance crystal f ref out 16 f ref in 15 13 pf 13 pf f ref out 16 f ref in 15 13 pf 13 pf 20 0 1000 10 5.0 0 gain (db) total esr ( w ) maximum esr ( ) crystal load capacitance (pf) s ta r t up tim e ( ms ) total esr ( w ) v cc = 3.6 v t a = 25 c figure 37. reference oscillator open loop gain versus frequency figure 38. reference oscillator open loop phase versus frequency figure 39. reference oscillator startup time versus total esr inactive to rx mode figure 40. reference oscillator open loop gain versus esr figure 41. maximum esr versus crystal load capacitance (c1 = c2) v cc = 3.6 v t a = 25 c 4.0 3.0 2.0 1.0 0 50 100 150 200 250 300 350 2.048 mhz 5.12 mhz 16 12 8.0 4.0 0 50 100 150 200 250 300 350 100 10 12 14 16 18 20 22 24 26 28 30 32 w 70 5.0 c1 and c2 (pf) crystal load capacitance (pf) figure 42. optimum values for c1, c2 versus equivalent required parallel capacitance 60 50 40 30 20 10 0 10 15 20 25 30 35
mc33411a/b 28 motorola rf/if device data table 5. mcu clock divider programming mcu clk bit #16 mcu clk bit #15 mcu clk bit #14 clk out divider value 0 0 0 2.0 0 0 1 3.0 0 1 0 4.0 0 1 1 5.0 1 0 0 2.5 1 0 1 20 1 1 0 80 1 1 1 312.5 table 6. mcu clock divider frequencies crystal clock output divider crystal frequency 2.0 2.5 3.0 4.0 5.0 20 80 312.5 10.24 mhz 5.12 mhz 4.096 mhz 3.413 mhz 2.56 mhz 2.048 mhz 512 khz 128 khz 32.768 khz 11.15 mhz 5.575 mhz 4.46 mhz 3.717 mhz 2.788 mhz 2.23 mhz 557 khz 139 khz 35.68 khz 12 mhz 6.0 mhz 4.8 mhz 4.0 mhz 3.0 mhz 2.4 mhz 600 khz 150 khz 38.4 khz transmit and receive (lo1) pll sections the transmit and receive plls (pins 69 and 14, respectively) are designed to be part of a 900 mhz system. in a typical application the transmit pll section will be set up to generate the transmit frequency, and the receive pll section will be set up to generate the lo1 frequency. the two sections are identical, and function independently. external requirements for each include a lowpass filter, a 900 mhz vco, and a 64/65 or 128/129 dual modulus prescaler. the frequency output of the vco is to be reduced by the dual modulus prescaler, and then input to the mc33411 (at pin 8 or 2). that frequency is then further reduced by the programmable 13bit counter (bits 1/197 or 2/197), and provided to one side of the phase detector, where it is compared with the pll reference frequency. the output of the phase detector (at pin 6 or 4) is a threestate charge pump which drives the vco through the lowpass filter. bits 1/20 and 2/20 set the gain of each of the two charge pumps to either 100/2 p m a/radian or 400/2 p m a/radian. the polarity of the two phase detector outputs is set with bits 1/21 and 2/21. if the bit = 0, the appropriate pll is configured to operate with a noninverting lowpass filter/vco combination. if the lowpass filter/vco combination is inverting, the polarity bit should be set to 1. the 7bit a and a' counters (bits 1/60 and 2/60) are to be set to drive the modulus control input of the 64/65 or 128/129 dual modulus prescalers. the modulus control outputs (pins 9 and 1) can be set to either a voltage mode (logic 1) or a current mode (logic 0) with bit 3/16. to calculate the settings of the n and a registers, the following procedure is used: f vco f pll nt (nt must be an integer) nt p n (1) (2) a = remainder of equation 2 (decimal part of n x p) (3) where: f vco = the vco frequency f pll = the pll reference frequency set within the mc33411 p = the smaller divisor of the dual modulus prescaler (64 for a 64/65 prescaler) n = the whole number portion is the setting for the n (or n') counter within the mc33411 a = the setting for the a (or a') counter within the mc33411 for example, if the vco is to provide 910 mhz, and the internal pll reference frequency is 50 khz, then the equations yield: nt 910 x 10 6 50 x 10 3 18, 200 n 18, 200 64 284.375 a 0.375 x 64 24 the n register setting is 284 (0 0001 0001 1100), and the a register setting is 24 (001 1000).
mc33411a/b 29 motorola rf/if device data 2nd lo (lo2) this pll is designed to be the 2nd local oscillator in a typical 900 mhz system, and is designed for frequencies up to 80 mhz. the vco and varactor diodes are included, and are to be used with an external tank circuit (pins 4345). bits 4/2018 are used to select an internal capacitor, with a value in the range of 0 to 7.6 pf, to parallel the varactor diodes and the tank's external capacitor. this permits a certain amount of fine tuning of the oscillator's performance. see table 7. a buffered output is provided to drive, e.g., a mixer. the frequency is set with the programmable 14bit counter (bits 3/130) in conjunction with the pll reference frequency. for example, if the reference frequency is 50 khz, and the 2nd lo frequency is to be 63.3 mhz, the 14bit counter needs to be set to 1266 d (00 0100 1111 0010). the output level is dependent on the value of the impedance at pin 41, partly determined by the external pullup resistor. the output of the phase detector is a threestate charge pump which drives the varactor diodes through an external lowpass filter. bit 3/14 sets the gain of the charge pump to either 100/2 p m a/radian (logic 0) or 400/2 p m a/radian (logic 1). bit 3/15 sets its polarity if 0, the pll is configured to operate with a noninverting lowpass filter/vco combination. if the lowpass filter/vco combination is inverting, the polarity bit should be set to 1. please note that the 2nd lo vco on the mc33411 is of the noninverting type. figures 43 through 45 describe the response of the 2nd lo. table 7. lo2 capacitor select programming lo2 capacitor select bit #20 lo2 capacitor select bit #19 lo2 capacitor select bit #18 select # lo2 capacitor select value 0 0 0 0 0 pf 0 0 1 1 1.1 pf 0 1 0 2 2.2 pf 0 1 1 3 3.3 pf 1 0 0 4 4.3 pf 1 0 1 5 5.4 pf 1 1 0 6 6.5 pf 1 1 1 7 7.6 pf
mc33411a/b 30 motorola rf/if device data figure 43. varicap capacitance versus control voltage minimum overall q 80 0 coil inductance (nh) 70 60 50 40 30 20 10 0 200 400 600 800 1000 120 0 30 mhz 80 mhz 60 mhz v cc = 3.6 v t a = 25 c figure 44. minimum overall q versus coil inductance for lo2 lo amplitude (dbmv) 35 0 tank resistance ( w ) v cc = 3.6 v t a = 25 c f lo = 63.3 mhz 30 25 20 15 10 5 0 500 1000 1500 2000 2500 3000 3500 6.0 16 0 c apa c ita nce ( p f) control voltage (v) 15 14 13 12 11 10 9.0 8.0 7.0 123456 v cc = 3.6 v t a = 25 c figure 45. lo2 amplitude versus overall tank parallel resistance
mc33411a/b 31 motorola rf/if device data loop filter characteristics let's consider the following discussion on loop filters. the fundamental loop characteristics, such as capture range, loop bandwidth, lockup time, and transient response are controlled externally by loop filtering. figure 46 is the general model for a phase lock loop (pll). phase detector (k pd ) filter (k f ) vco (k o ) fo divider (k n ) fi figure 46. pll model where: k pd = phase detector gain constant k f = loop filter transfer function k o = vco gain constant k n = divide ratio (n) fi = input frequency fo = output frequency fo/n = feedback frequency divided by n from control theory the loop transfer function can be represented as follows: a k pd k f k o k n open loop gain k pd can be either expressed as being 200 m a/4 p or 800 m a/4 p . more details about performance of different type pll loops, refer to motorola application note an535. the loop filter can take the form of a simple low pass filter. a current output, type 2 filter will be used in this discussion since it has the advantage of improved step response, velocity, and acceleration. the type 2 low pass filter discussed here is represented as follows: from phase detector to vco r2 c2 c1 figure 47. loop filter with additional integrating element from figure 47, c apacitor c1 forms an additional integrator, providing the type 2 response, and filters the discrete current steps from the phase detector output. the function of the additional components r2 and c2 is to create a pole and a zero (together with c1) around the 0 db point of the open loop gain. this will create sufficient phase margin for stable loop operation. in figure 48, the open loop gain and the phase is displayed in the form of a bode plot. since there are two integrating functions in the loop, originating from the loopfilter and the vco gain, the open loop gain response follows a second order slope (40 db/dec) creating a phase of 180 degrees at the lower and higher frequencies. the filter characteristic needs to be determined such that it is adding a pole and a zero around the 0 db point to guarantee sufficient phase margin in this design (qp in figure 48). phase figure 48. bode plot of gain and phase in open loop condition a , o pe n loo p g a in w p open loop gain q p 180 90 0 0 the open loop gain including the filter response can be expressed as: a openloop k pd k o (1 j (r2c2) ) j k n j 1 j r2c1c2 c1 c2 (4) the two time constants creating the pole and the zero in the bode plot can now be defined as: t1 r2c1c2 c1 c2 t2 r2c2 (5) by substituting equation (5) into (4), it follows: a openloop k pd k o t1 2 c1k n t2 1 j t2 1 j t1 (6) the phase margin (phase + 180) is thus determined by: q p arctan ( t2 ) arctan ( t1 ) (7) at w = w p , the derivative of the phase margin may be set to zero in order to assure maximum phase margin occurs at w p (see also figure 48). this provides an expression for w p : dq p d 0 t2 1 ( t2 ) 2 t1 1 ( t1 ) 2 (8) p 1 t2t1 (9) or rewritten: t1 1 p 2 t2 (10) by substituting into equation (7), solve for t2: t2 tan q p 2 4 p (11)
mc33411a/b 32 motorola rf/if device data by choosing a value for w p and q p , t1 and t2 can be calculated. the choice of q p determines the stability of the loop. in general, choosing a phase margin of 45 degrees is a good choice to start calculations. choosing lower phase margins will provide somewhat faster locktimes, but also generate higher overshoots on the control line to the vco. this will present a less stable system. larger values of phase margin provide a more stable system, but also increase locktimes. the practical range for phase margin is 30 degrees up to 70 degrees. the selection of w p is strongly related to the desired locktime. since it is quite complicated to accurately calculate lock time, a good first order approach is: t_lock 3 p (12) equation (12) only provides an order of magnitude for lock time. it does not clearly define what the exact frequency difference is from the desired frequency and it does not show the effect of phase margin. it assumes, however, that the phase detector steps up to the desired control voltage without hesitation. in practice, such step response approach is not really valid. if the two input frequencies are not locked, their phase maybe momentarily zero and force the phase detector into a high impedance mode. hence, the lock times may be found to be somewhat higher. in general, w p should be chosen far below the reference frequency in order for the filter to provide sufficient attenuation at that frequency. in some applications, the reference frequency might represent the spacing between channels. any feedthrough to the vco that shows up as a spur might affect adjacent channel rejection. in theory, with the loop in lock, there is no signal coming from the phase detector. but in practice small current pulses and leakage currents will be supplied to both the vco and the phase detector. the external capacitors may show some leakage, too. hence, the lower w p , the better the reference frequency is filtered, but the longer it takes for the loop to lock. as shown in figure 48, the open loop gain at w p is 1 (or 0 db), and thus the absolute value of the complex open loop gain as shown in equation (6) solves c1: c1 k pd k o t1 2 k n t2 1 p t2 2 1 p t1 2 (13) with c1 known, and equation (5) solve c2 and r2 : c2 c1 t2 t1 1 (14) r2 t2 c2 (15) the vco gain is dependent on the selection of the external inductor and the frequency required. the free running frequency of the vco is determined by: f 1 2 lc t (16) in which l represents the external inductor value and c t represents the total capacitance (including internal capacitance) in parallel with the inductor. the vco gain can be easily calculated via the internal varicap transfer curve shown in figure 43. as can be derived from figure 43, the varicap capacitance changes 2.0 pf over the voltage range from 1.0 v to 3.0 v: cvar 2.0 pf 2.0 v (17) combining (16) with (17) the vco gain can be determined by: k o 1 j2.0v 1 2 lc t 1 2 l c t cvar 2
(18) although the basic loopfilter previously described provides adequate performance for most applications, an extra pole may be added for additional reference frequency filtering. given that the channel spacing is based on the reference frequency, and any feedthrough to the first lo may effect parameters like adjacent channel rejection and intermodulation. figure 49 shows a loopfilter architecture incorporating an additional pole. from phase detector to vco r2 c2 c1 figure 49. loop filter with additional integrating element c3 r3 for the additional pole formed by r3 and c3 to be efficient, the cutoff frequency must be much lower than the reference frequency. however, it must also be higher than w p in order not to compromise phase margin too much. the following equations were derived in a similar manner as for the basic filter previously described.
mc33411a/b 33 motorola rf/if device data similarly, it can be shown: a openloop k pd k o k n 2 ( c1 c2 c3 ) 2 c1c2c3r2r3 1 j t2 1 j t1 (19) in which: t1 ( c1 c2 ) t2 ( c1c2 ) t3 c1 c2 c3 2 c1t2t3 (20) t2 r2c2 t3 r3c3 (22) (21) from t1 it can be derived that: c2 ( t1 t2 ) c3 c1 t2 t3 t1 2 t1t2t3 t3 t1 (23) in analogy with (13), by forcing the loopgain to 1 (0 db) at w p , we obtain: c1 ( t1 t2 ) c2t3 c3t2 k pd k o k n p 2 1 p t2 2 1 p t1 2 (24) solving for c1: c1 ( t2 t1 ) t3c3 ( t3 t1 ) t2c3 ( t3 t1 ) k pd k o t1 p 2 k n 1 p t2 2 1 p t1 2 ( t3 t1 ) t2 ( t3 t1 ) t3 t2 t3 t1 p 2 t1t2t3 t3 (25) by selecting w p via (12), the additional time constant expressed as t3, can be set to: t3 1 k p (26) the kfactor shown determines how far the additional pole frequency will be separated from w p . selecting too small of a kfactor, the equations may provide negative capacitance or resistor values. too large of a kfactor may not provide the maximum attenuation. by selecting r3 to be 100 k w , c3 becomes known and c1 and c2 can be solved from the equations. by using equations (11) and (10), time constants t2 and t1 can be derived by selecting a phase margin. finally, r2 follows from t2 and c2. a test circuit with the following components and conditions was constructed with these results: loop filter (see figure 49): c1 = 470 pf r2 = 68 k w c2 = 3.9 nf r3 = 270 k w c3 = 82 pf lo2 tank: ctotal = 39.3 pf lext = 150 nh, q = 50 @ 250 mhz reference frequency = 10.24 mhz (unadjusted) r counter = 205 lo2 counter = 1266 ac load = 25 w frequency of lo2 = 63.258 mhz phase noise @ 50 khz offset = 107 dbc sidebands @ 50 khz & 100 khz offsets = 69 dbc low battery/ rssi voltage measurement both the low battery (bits 5/2318) and rssi (bits 5/1712) measurement circuits have a 6bit a/d converter whose value may be read back via the spi. the a/d's sample their voltages at a frequency equal to the internal scf clock frequency divided by 128. the low battery measurement a/d senses and divides by 2.5 the supply voltage (at pin 23). please note that the minimum low battery detect (lbd) voltage is 2.7 v, since there is no guarantee that the device will operate below this value. the rssi measurement senses the voltage at pin 37.
mc33411a/b 34 motorola rf/if device data these values are compared to the internal reference vb ( 1.5 v) which is available at pin 37. the value read back from the lbd a/d will therefor be approximately: n(for lbd) 63 (v cc ) 2.5(vb)(1.07) (27) and for the rssi n(for rssi) 63 (rssivoltage) (vb)(1.07) (28) vb voltage adjust and characteristics vb has a production tolerance of 8%, and can be adjusted over a 9% range using bits 3/2017. the adjustment steps will be 1.2% each (see table 8). if desired, vb can be used to bias external circuitry, as long as the load current on this pin does not exceed 10 m a. v b varies by less than 0.5% over supply voltage, referenced to v cc = 3.6 v. the value of the decoupling capacitor connected from vb to ground affects both the noise and crosstalk from the receive and transmit audio paths, so the value should be chosen with caution. figures 50 and 51 show this relationship. table 8. vb voltage reference programming v ref adjust bit #20 v ref adjust bit #19 v ref adjust bit #18 v ref adjust bit #17 v ref adjust # voltage reference adjustment amount 0 0 0 0 0 9.0% 0 0 0 1 1 7.8% 0 0 1 0 2 6.6% 0 0 1 1 3 5.4% 0 1 0 0 4 4.2% 0 1 0 1 5 3.0% 0 1 1 0 6 1.8% 0 1 1 1 7 0.6% 1 0 0 0 8 0.6% 1 0 0 1 9 1.8% 1 0 1 0 10 3.0% 1 0 1 1 11 4.2% 1 1 0 0 12 5.4% 1 1 0 1 13 6.6% 1 1 1 0 14 7.8% 1 1 1 1 15 9.0% 0.01 125 105 0.01 crosstalk (db) vb capacitor ( m f) 110 115 120 0.1 1.0 10 50 vb capacitor ( m f) noise figure 50. crosstalk/noise from c in to e out versus vb capacitor figure 51. crosstalk/noise from e in to tx out versus vb capacitor 107 87 92 97 102 noise level @ e out (dbv) crosstalk, 130 w load crosstalk, no load 0.1 1.0 10 crosstalk (db) 55 60 65 70 75 80 85 90 95 75 63 67 71 73 69 65 61 noise level @ tx out (dbv) noise crosstalk v cc = 3.6 v t a = 25 c v cc = 3.6 v t a = 25 c
mc33411a/b 35 motorola rf/if device data mcu serial interface the mcu serial interface is a 3wire interface, consisting of a clock line, an enable line, and a bidirectional data line. the interface is always active, i.e., it cannot be powered down as all other sections of the mc33411 are disabled and enabled through this interface. after the device powerup (or whenever a reset condition is required), the mcu should perform the following steps: 1. initialize the data line to a high impedance state. 2. initialize the clock line to a logic low. 3. initialize the enable line to a logic low. 4. pulse the clock line a minimum of once (rz format) while leaving the enable line continuously low. this places the spi port into a known condition. 5. load all registers with their desired initial values. the clock (returntozero format) must be supplied to the mc33411 at pin 11 to write or read data, and can be any frequency up to 2.0 mhz. the clock need not be present when data is not being transferred. the enable line must be low when data is not being transferred. internally there are 7 data registers, 24bits each, addressed with 4bits ranging from $h1 to $h7 (see tables 9 and 10). register 5, bits 2312 are readonly bits, while all other register bits are read/write. all unused/unimplemented bits are reserved for motorola use only. the contents of the 7 registers can be read out at any time. all bits are written in, or read out, on the clock's positive transition. the write and read operations are as follows: figure 52. writing data to the mc33411 clock data enable 123 24 4bit address 24bit data from mcu msb lsb latch address latch data a. write operation: to write data to the mc33411, the following sequence is required (see figure 52): 6. the enable line is taken high. 7. five bits are entered: the first bit must be a 0 to indicate a write operation. the next four bits identify the register address (00010111). the msb is entered first. 8. the enable line is taken low. at this transition, the address is latched in and decoded. 9. the enable line is maintained low while the data bits are clocked in. the msb is entered first, and the lsb last. if 24bits are written to a register which has less than 24 active bits (e.g., register 6), the unassigned bits are to be 0. 10. after the last bit is entered, the enable line is to be taken high and then low. the falling edge of this pulse latches in the just entered data. the clock line must be at a logic low and must not transition in either direction during this enable pulse. 11.the enable line must then be kept low until the next communication. note: if less than 24 bits are to be written to a data register, it is not necessary to enter the full 24 bits, as long as they are all lower order bits. for example, if bits 06 of a register are to be updated, they can be entered as 7 bits with 7 clock cycles in step 4 above. however, if this procedure is used, a minimum of 4 bits, with 4 clock pulses, must be entered.
mc33411a/b 36 motorola rf/if device data figure 53. reading data from the mc33411 clock data enable 123 24 sets data pin to output 4bit address 24bit data from mc33411 msb lsb latch address and load data into shift register sets data pin to input b. read operation: to read the output bits (bits 5/2312), or the contents of any register, the following sequence is required (see figure 53): 1. the enable line is taken high. 2. five bits are entered: the first bit must be a 1 to indicate a read operation. the next four bits identify the register address (00010111). the msb is entered first. 3. the enable line is taken low. at this transition, the address is latched in and decoded, and the contents of the selected register is loaded into the 24bit output shift register. at this point, the data line (pin 12) is still an input. 4. while maintaining the enable line low, the data is read out. the first clock rising edge will change the data line to an output, and the msb will be present on this line. 5. the full contents of the register are then read out (msb first, lsb last) with a total of 24 clock rising edges, including the one in step 4 above. it is recommended that the mcu read the bits after the clock's falling edge. 6. after the last clock pulse, the enable line is to be taken high and then low. the falling edge of this pulse returns the data pin to be an input. the clock line must be at a logic low and must not transition in either direction during this enable pulse. 7. the enable line must then be kept low until the next communication. power supply/power saving modes the power supply voltage, applied to all v cc pins, can range from 2.7 to 5.5 v. all v cc pins must be within 0.5 v of each other, and each must be bypassed. it is recommended a ground plane be used, and all leads to the mc33411 be as short and direct as possible. to reduce the possibility of device latchup, it is highly recommended that the audio, synthesizer and rf v cc portions of the chip be isolated from the main supply through 10 to 25 w resistors (see the evaluation pcb schematic, figure 54). this also provides rftoaudio noise isolation. the supply and ground pins are distributed as follows: 1. pin 23 provides power to the audio section. pin 40 is the ground pin. 2. pin 28 provides power to the speaker amplifier section. pin 31 is the ground pin. 3. pin 3 provides power to the rx pll section. pin 5 is the ground pin. 4. pin 7 provides power to the tx pll section, and the mcu interface. pin 5 is the ground pin. 5. pin 42 provides power to the 2nd lo section. pins 46 and 48 are the ground pins. 6. pin 14 is the ground pin for the digital circuitry. power for the digital circuitry is derived from pin 23. to conserve power, various sections can be individually disabled by using bits 5/70 and 6/7 (setting a bit to 1 disables the section). 1. reference oscillator disable (bit 5/0) the reference oscillator at pins 15 and 16 is disabled, thereby denying a clock to the three plls and the switched capacitor filters. this function is not available on the abo version. 2. tx pll disable (bit 5/1) the 13bit and 7bit counters, input buffer, phase detector, and modulus control blocks are disabled. the charge pump output at pin 6 will be in a hiz state. 3. rx pll disable (bit 5/2) the 13bit and 7bit counters, input buffer, phase detector, and modulus control blocks are disabled. the charge pump output at pin 4 will be in a hiz state. 4. lo2 pll disable (bit 5/3) the vco, 14bit counter, output buffer, and phase detector are disabled. the charge pump output at pin 47 will be in a hiz state. 5. power amplifier disable (bit 5/4) the two speaker amplifiers are disabled. their outputs will go to a high impedance state. 6. rx audio path disable (bit 5/5) the antialiasing filter, lowpass filter, and variable gain stage are disabled. 7. tx audio path disable (bit 5/6) disables the microphone amplifier and lowpass filter. 8. low battery/rssi measurement disable (bit 5/7) both 6bit a/ds are disabled. 9. data slicer disable (bit 5/8) the data slicer is disabled and ds out goes to high impedance. 10. mcu clock disable (bit 6/7) the mcu clock counter is disabled and the mcu clock output will be in a hiz state. this function is not available on the abo version. note: the 12bit reference counter is disabled if the three plls are disabled (bits 5/13 = 1).
mc33411a/b 37 motorola rf/if device data table 9. register map table 10. register map: powerup defaults 0111 7 volume control tx gain adjust rx gain adjust rssi & batt. a/d disable 0001 0010 0011 0100 0101 0110 0111 reg add reg num msb bit 23 lsb bit 0 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 1 2 3 4 5 6 7 tx polarity select rx polarity select tx pd cur sel rx pd cur sel msb msb lsb lsb lsb lsb 13bit tx n counter divide value 13bit rx n' counter divide value msb msb vb voltage reference adjust ftxmc/ frxmc mode lo2 polarity select 2nd lo pd cur sel lsb 14bit 2nd lo counter divide value msb test modes lo2 capacitor select 6bit switched capacitor filter counter divide value msb lsb 12bit reference counter divide value 6bit battery voltage a/d output 6bit rssi a/d output mcu clock divide select volume control tx gain adjust rx gain adjust side tone attenuate select unused register bits data slicer invert data slicer disable tx audio disable rx audio disable power amp disable 2nd lo pll disable rx pll disable tx pll disable ref osc disable* alc gain = 25 alc gain = 10 comp. low max. gain en. mcu clk disable* alc disable limiter disable compres ser pass through expander pass through tx mute rx mute power amp mute 7bit tx a counter divide value 7bit rx a' counter divide value rssi & batt. a/d disable 0001 0010 0011 0100 0101 0110 reg add reg num msb bit 23 lsb bit 0 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 1 2 3 4 5 6 tx polarity select rx polarity select tx pd cur sel rx pd cur sel msb msb lsb lsb lsb lsb 13bit tx n counter divide value 13bit rx n' counter divide value msb msb vb voltage reference adjust ftxmc/ frxmc mode lo2 polarity select 2nd lo pd cur sel lsb 14bit 2nd lo counter divide value msb test modes lo2 capacitor select 6bit switched capacitor filter counter divide value msb lsb 12bit reference counter divide value 6bit battery voltage a/d output 6bit rssi a/d output side tone attenuate select unused register bits data slicer invert data slicer disable tx audio disable rx audio disable power amp disable 2nd lo pll disable rx pll disable tx pll disable ref osc disable* alc gain = 25 alc gain = 10 comp. low max. gain en. mcu clk disable* alc disable limiter disable compres ser pass through expander pass through tx mute rx mute power amp mute 7bit tx a counter divide value 7bit rx a' counter divide value 001000 00000000010 00000 001000 00000000010 00000 01110 00 1 00000 000 00 0 00 000010 00001000000 00000 0000000 00000 00000000 00000 0 11011101111 01111 0 0 table 9. register map table 10. register map: powerup defaults * these bits not included in obo version. * these bits not included in obo version. mcu clock divide select
mc33411a/b 38 motorola rf/if device data evaluation pcb the evaluation pcb is a versatile board which allows the mc33411 to be configured to analyze individual operating parameters or the complete audio transmit and receive paths. the general purpose schematic and associated parts list for the pcb are given in figure 54. with the jumpers positioned as shown in the parts list (either shunt or open). the pcb is configured to analyze complete transmit and receive audio paths. parts lists as ouser definedo can be installed to analyze other functions of the device. table 11 lists these devices along with their respective functions. table 11. component(s) function notes r20 microphone bias r19,j24,j27 preemphasis/deemphasis r3,c7,j5 detector lowpass filter (lpf) r4,c8 data slicer lpf l1,c21 2nd lo tank see equations 16 and 17 c18,r9,c19,r10,c20 2nd lo lpf see eq. 10, 11, 12, 21, 23, 25, and 26 c26,r13,c27,r14,c28 rx 1st lo lpf see eq. 10, 11, 12, 21, 23, 25, and 26 c22,r11,c23,r12,c24 tx 1st lo lpf see eq. 10, 11, 12, 21, 23, 25, and 26
mc33411a/b 39 motorola rf/if device data figure 54. figure 54. mc33411a/b evaluation pcb schematic 0.01 v cca v ccr v ccl pa in e in lo2 ctl lo2 out aud in jp3 h5x2 pa out+ pa out tx aud c in lim in v ccd gnd tp7 tp6 f in v ccd r x o u t rssi in e i n e c a p e o u t p a i g n d p a p a o p a o + v c c p a v b v a g m c i f r x m c f r x p l l v c c r x p d p l l g n d t x p d p l l v c c f t x f t x m c e n c l k d a t a rx audio in ds in gnd audio lo2 out lo2 v cc lo2+ lo2 ctl lo2 lo2 gnd lo2 pd lo2 gnd mic amp v cc audio c in c cap c out lim in tx out ds out mcu clk out gnd digital f ref out f ref in 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 1 234 56789 1 0 1 1 1 2 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 det in rssi rx en rx pd rx mc frx jp1 jp2 h5x2 h5x2 ftx tx mc tx pd tx en tx out tx dat tx dat tx en rx en en clk data ck out ds out r6 47.5 k j27 n/o j25 n/c j26 n/c r5 47.5 k c13 220 p r7 130 j8 n/o c12 1.0 c10 1.0 v cca j6 n/c v cca c38 4.7 0.1 c39 r19 u/d u/d r20 v cca 1.0 c1 r1 47.5 k j23 n/c j24 n/o c2 220 p r2 47.5 k j2 n/c j3 n/c c3 c4 c5 1.0 1.0 0.47 j11 n/c j12 n/c j13 n/o y1 10 m c15 27 p c16 27 p r8 49.9 c17 0.01 c30 10 c31 0.01 d1 c32 10 c34 10 c36 10 c33 0.01 c35 0.01 c37 0.01 j5 n/o r3 u/d c7 u/d r4 u/d c8 u/d c14 c6 c9 c40 1.0 1.0 0.01 v ccl v ccl r18 49.9 l1 u/d c21 u/d r10 u/d r9 u/d c19 u/d c18 u/d c20 u/d j15 n/c v ccr c26 u/d c27 u/d c28 u/d r13 u/d r14 u/d r12 u/d r11 u/d c22 u/d c23 u/d c24 u/d c25 0.01 c29 0.01 v cca j7 n/c c12 1.0 r15 10 r16 10 r17 10 1n4001 j14 tp2 tp1 j1 j10 j9 j17 j18 tp4 tp3 j4 j16 tp5 u1 mc33411
mc33411a/b 40 motorola rf/if device data figure 55. mc33411a/b evaluation pcb component side c1,c3,c5,c6,c9,c10,c12 1.0 c13,c2 220 p c4,c11 0.47 l1,r3,r4,c7,c8,r9,r10, user defined r11,r12,r13,r14,c18,r19, c19,r20,c20,c21,c22,c23, c24,c26,c27,c28 c14,c17,c25,c29,c31,c33, 0.01 c35,c37,c40 c15,c16 27 p c30,c32,c34,c36 10 c38 4.7 c39 0.1 d1 1n4001 jp1,jp2,jp3 header, 5x2 j1,j4,j9,j10 audiojack switchcroft 3501fp j2,j3,j6,j7,j11,j12,j15, j23,j25,j26 shunt j5,j8,j13,j24,j27 open j14,j16 sma ef johnson 1420701201 j17,j18 bananna johnson components 1080902001 r1,r2,r5,r6 47.5 k r7 130 r8,r18 49.9 r15,r16,r17 10 u1 mc33411afta or MC33411Bfta y1 10 m raltron a10.00018 4.5 4.5 default units: microfarads, microhenries, and ohms
mc33411a/b 41 motorola rf/if device data figure 56. mc33411a/b evaluation pcb solder side 4.5 4.5
mc33411a/b 42 motorola rf/if device data fta suffix plastic package case 93202 (lqfp48) issue e outline dimensions ??? ??? ??? a a1 z 0.200 ab tu 4x z 0.200 ac tu 4x b b1 1 12 13 24 25 36 37 48 s1 s v v1 p ae ae t, u, z detail y detail y base metal n j f d tu m 0.080 z ac section aeae ad g 0.080 ac m top & bottom l w k aa e c h 0.250 r 9 detail ad notes: 1 dimensioning and tolerancing per asme y14.5m, 1994. 2 controlling dimension: millimeter. 3 datum plane ab is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4 datums t, u, and z to be determined at datum plane ab. 5 dimensions s and v to be determined at seating plane ac. 6 dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 per side. dimensions a and b do include mold mismatch and are determined at datum plane ab. 7 dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.350. 8 minimum solder plate thickness shall be 0.0076. 9 exact shape of each corner is optional. t u z ab ac gauge plane dim a min max 7.000 bsc millimeters a1 3.500 bsc b 7.000 bsc b1 3.500 bsc c 1.400 1.600 d 0.170 0.270 e 1.350 1.450 f 0.170 0.230 g 0.500 bsc h 0.050 0.150 j 0.090 0.200 k 0.500 0.700 m 12 ref n 0.090 0.160 p 0.250 bsc l 1 5 r 0.150 0.250 s 9.000 bsc s1 4.500 bsc v 9.000 bsc v1 4.500 bsc w 0.200 ref aa 1.000 ref
mc33411a/b 43 motorola rf/if device data motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, represe ntation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the applicati on or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo para meters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all ope rating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under it s patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical imp lant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product cou ld create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expens es, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motoro la, inc. motorola, inc. is an equal opportunity/affirmative action employer. mfax is a trademark of motorola, inc. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : motorola japan ltd.; spd, strategic planning office, 141, p.o. box 5405, denver, colorado 80217. 13036752140 or 18004412447 4321 nishigotanda, shinagawaku, tokyo, japan. 813 54878488 customer focus center: 18005216274 mfax ? : rmfax0@email.sps.mot.com touchtone 1 6022446609 asia / pacific : motorola semiconductors h.k. ltd.; silicon harbour centre, motorola fax back system us & canada only 18007741848 2, dai king street, tai po industrial estate, tai po, n.t., hong kong. http://sps.motorola.com/mfax/ 85226668334 home page : http://motorola.com/sps/ mc33411a/d ?

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